Modern integrated circuits (ICs) are usually designed using CMOS technology. Some of the advantages of using CMOS instead of other technologies such as bipolar are smaller circuit geometries and lower power consumption. In the past decades, IC design and fabrication technology has advanced such that millions of transistors can be fabricated on a single integrated circuit. While each transistor may only consume a very small amount of power, that miniscule amount of power consumption becomes quite high in a multi-million transistor IC. In many battery operated applications, such as cellular phones, notebook PCs (Personal Computers), PDAs (Personal Digital Assistants), MP3 players, digital cameras and camcorders, it is highly desirable to reduce power consumption, thereby extending the time such portable electronic device can operate for each recharge. For some other high performance applications, such as microprocessors, it is very important to find a way to reduce the power consumption because the high frequency clock driving those ICs leads to higher power consumption, which requires elaborate and expansive means to dissipate the heat generated. For example, the monthly electricity bill for computer server farm is a significant portion of the operator's expenses.
Power integrity is also important to designers of integrated circuits. Current is supplied to the transistors of an IC through power grids. The local voltage of each transistor may be affected by the voltage drop from the power source according to Ohm's Law (delta V=I*R where delta V is the voltage drop, I is current and R is resistance). If certain portions (sometimes referred to as blocks) of the IC consume too much power at any given instant, the voltage for this block or its neighboring transistors may drop below the threshold voltage for the device to operate reliably. Designers must understand the power grid design and the power consumption profile to ensure that the IC being designed can operate reliably under the intended application environment. Prior art power analysis techniques are either inaccurate, cannot provide enough detail to be useful, or both.
The power consumed by an IC can be divided as either static power consumption or dynamic power consumption. Static power consumption is the power the IC consumes when the IC is powered on but not doing anything (none of the signals are toggling between logic level high (“one”) and logic level low (“zero”)). Static power consumption is usually caused by leakage current flowing through transistors. In contrast, dynamic power consumption is the power an IC consumes while the circuit is actually operating. Dynamic power consumption is usually caused by transistor switching activity. Each time a logic gate changes state (i.e., from a one to a zero or vice-versa), it has to charge or discharge the associated parasitic capacitance. In addition, there is a small time period during the state transition that both the nFET and pFET are turned on which results an instantaneous feed-thru current. In general, dynamic power consumption is far greater than static power for most CMOS ICs.
In general, dynamic power consumption in a CMOS circuit is proportional to the frequency of state transitions. Most dynamic power analysis is based on the transition activities of the IC being analyzed, often referred to as the design under test (“DUT”). This information is usually obtained by simulating the operation of the DUT stimulated by test vectors or a test bench provided by the designer of the IC. Simulation is performed using tools referred to as simulators (sometimes referred to as software simulators). Simulator is a software program that models behavior of integrated circuit designs in a computer/workstation. In conjunction with the physical design attributes (i.e., layout and routing) of the IC, the dynamic power consumption of an IC can be calculated. Using the simulation tool, the designer can analyze the result and determine if the design has met the power consumption limits required for the IC design.
Because of the extensive computations involved when using prior power estimation tools, many designers choose to perform power consumption analysis using average power consumption. FIG. 1 is a graph showing an example of power consumption over a certain period of time. The X axis of this graph (and the remaining power consumption graphs) shows the duration of time over which functional verification, i.e., emulation or simulation, of a circuit takes place. The Y axis of this power graph (and the remaining power consumption graphs) shows the actual power consumption. As can be seen in FIG. 1, the actual power consumption of a DUT, seen in curve 10, can have multiple peaks that exceed the average power level, which is illustrated by curve 15 (which is a straight line). Because the average power consumption does not reflect the actual power consumption at particular times, many circuit designers take the value for average power consumption and add a safety margin, for example fifty percent, to compensate for the fluctuation in actual power consumption. Such assumptions can be wrong and result in a product that is either too costly due to over design or fail to operate reliably during peak consumption due to IR drop, overheating or other problems. With prior art power estimation methods using simulation, circuit designers usually had no choice but to accept these compromises.
One type of electronic design automation tool is the hardware-based functional verification system, e.g., hardware logic emulation systems and simulation accelerators (for simplicity, both emulation systems and hardware based simulation acceleration systems may be referred as emulation systems in the subsequent discussion). Emulation systems are used to verify the functionalities of electronic circuit designs prior to fabrication as chips or as electronic systems. Typical emulation systems utilize either interconnected programmable logic chips or interconnected processor chips. Examples of hardware logic emulation systems using programmable logic devices can be seen in, for example, U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191. U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191 are incorporated herein by reference. Examples of hardware logic emulation systems using processor chips can be seen in, for example, U.S. Pat. Nos. 5,551,013, 6,035,117 and 6,051,030. U.S. Pat. Nos. 5,551,013, 6,035,117 and 6,051,030 are incorporated herein by reference.
The DUT is usually provided in the form of either RTL (Register Transfer Level) description or gate level netlist (or “netlist” as it is referred to by those of ordinary skill in the art). The gate level netlist may have been derived from RTL sources, including from a hardware description language (HDL), such as Verilog or VHDL, using a method called synthesis. Both RTL and gate level netlists are descriptions of the circuit's components and electrical interconnections between the components. The components include all those circuit elements, such as combinatory logic (e.g., gates) and sequential logic (e.g., flip-flops and latches), necessary for implementing a logic circuit.
Until now, hardware-based functional verification systems such as emulation systems and simulation accelerators have been used to perform functional verification of logic designs. These hardware-based functional verification systems have certain advantages over software simulation tools. For example, as discussed, software simulation tools create models of user's design that are simulated in a computer workstation. All of these operations are conducted in a serial fashion with a single or a small number of CPUs. In contrast, hardware-based systems have dedicated hardware that will perform the designed functions in parallel. This massive parallelism enables a hardware-based system to operate at a speed that is orders of magnitude faster than a software simulator. Because emulators can operate so much faster than simulators, they can perform functional verification much faster. For example, an emulator can execute thousands of clock cycles of a DUT in a few milliseconds. Thus, in the same amount of time an emulator executes millions of clock cycles, a software simulator might only have simulated the execution of a few or even just a fraction of a clock cycle. In fact, emulators can operate at speed fast enough to allow the intended application software to run on the prototype system, which is something the software simulator can never accomplish.
Another advantage of hardware-based systems over simulation is their ability to operate “in circuit”. Operating “in circuit” refers to an emulator's ability to operate in the actual hardware that the DUT being emulated will eventually be installed into once it has been fabricated. This actual hardware is sometimes referred to as the “target system”. For example, the designer of a microprocessor might emulate the microprocessor design. Using a cable connecting the emulator to the motherboard of a personal computer, the emulator can be used in lieu of the actual microprocessor. The ability to operate in circuit provides many advantages. One of them is that the designer can see how their design functions in the actual system in which the DUT will eventually be installed. Another advantage is that in circuit emulation allows software development to take place before the IC chip is fabricated. Thus, the emulator can emulate the IC in the target system while the design team writes firmware and tests other application software.
As discussed, while simulators provide some level of information about the DUT's operation when used during power analysis, ICs being designed today will be operating in more complex environment with more stringent power consumption requirements than ever. Thus, there is a need for more sophisticated power analysis tools and methods that assist design engineers to understand power consumption problems better in order to reach their power consumption design objectives without too much guess work.
One of the major benefits of the present teaching is to enable the user to perform “What If” analysis. In the prior art, plotting a realistic power consumption graph is virtually impossible due to the performance limitations of the simulator. With hardware based verification system, this bottleneck is removed. The user now can try many different implementation options to determine which is best. The present teaching also allows the user to observe the impact of application software to power consumption therefore enable the user to tune the software for power optimization which is not practical with the prior arts.